%0 Conference Proceedings %T A Multi-Core AES Cryptoprocessor for Multi-Channel SDR %+ Laboratoire de l'intégration, du matériau au système (IMS) %+ Laboratoire Hubert Curien (LHC) %+ Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance (UMR 3192) (Lab-STICC) %A Grand, Michael %A Bossuet, Lilian %A Le Gal, Bertrand %A Dallet, Dominique %A Gogniat, Guy %< avec comité de lecture %( Proceedings of MCC2010 %B Military Communication and Information Systems Conference, MCC 2010 %C Wroclaw, Poland %P 1-7 %8 2010-09-27 %D 2010 %Z Computer Science [cs]/Embedded Systems %Z Computer Science [cs]/Cryptography and Security [cs.CR]Conference papers %X This paper presents a multi-core architecture for cryptographic processors. This architecture is specially designed for use in multi-channel Software Defined Radio Device. It provides support for GCM, CCM, CTR and other block cipher modes applied to AES algorithm. It can reach a maximum throughput around 2 Gbps. This paper also presents how partial reconfiguration could be used to improve flexibility of multi-core cryptoprocessors. %G English %L ujm-00552208 %U https://ujm.hal.science/ujm-00552208 %~ UNIV-ST-ETIENNE %~ UNIV-BREST %~ INSTITUT-TELECOM %~ IOGS %~ CNRS %~ UNIV-UBS %~ LAHC %~ IMS-BORDEAUX %~ PARISTECH %~ IMS-BORDEAUX-FUSION %~ LAB-STICC %~ UDL %~ INSTITUTS-TELECOM