Secured Reconfigurable Cryptographic Processor - Université Jean-Monnet-Saint-Étienne Access content directly
Conference Papers Year : 2010

Secured Reconfigurable Cryptographic Processor

Lubos Gaspar
  • Function : Author
  • PersonId : 881692
  • IdRef : 177548894

Abstract

This work presents reconfigurable processor aimed at symmetric-key cryptographic applications with architecture dedicated to the common cryptography tasks: 128-bit separated data and key registers, dedicated instruction set optimized for key generation and management, embedded cipher, etc. From the architecture point of view, the most important is the physical separation of data and key registers and buses, insuring that the confidential keys will never leave the system in clear. This way, the processor enables to separate red and black security zones easily. What is more, the goal is to achieve complete physical isolation of key management and data zones inside the single FPGA (required for security levels 3 and 4 as defined in FIPS-140-2 ).
No file

Dates and versions

ujm-00533246 , version 1 (05-11-2010)

Identifiers

  • HAL Id : ujm-00533246 , version 1

Cite

Lubos Gaspar, Viktor Fischer, Florent Bernard. Secured Reconfigurable Cryptographic Processor. PAca Security Trends In embedded Systems Workshop, PASTIS, Jun 2010, Gardanne, France. pp.NN. ⟨ujm-00533246⟩
55 View
0 Download

Share

Gmail Facebook X LinkedIn More