A Multi-Core AES Cryptoprocessor for Multi-Channel SDR - Université Jean-Monnet-Saint-Étienne
Communication Dans Un Congrès Année : 2010

A Multi-Core AES Cryptoprocessor for Multi-Channel SDR

Résumé

This paper presents a multi-core architecture for cryptographic processors. This architecture is specially designed for use in multi-channel Software Defined Radio Device. It provides support for GCM, CCM, CTR and other block cipher modes applied to AES algorithm. It can reach a maximum throughput around 2 Gbps. This paper also presents how partial reconfiguration could be used to improve flexibility of multi-core cryptoprocessors.

Domaines

Systèmes embarqués Cryptographie et sécurité [cs.CR]

Lilian Bossuet  : Connectez-vous pour contacter le contributeur

https://ujm.hal.science/ujm-00552208

Soumis le : mercredi 5 janvier 2011-16:42:35

Dernière modification le : mardi 27 août 2024-12:42:08

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Dates et versions

ujm-00552208 , version 1 (05-01-2011)

Identifiants

  • HAL Id : ujm-00552208 , version 1

Citer

Michael Grand, Lilian Bossuet, Bertrand Le Gal, Dominique Dallet, Guy Gogniat. A Multi-Core AES Cryptoprocessor for Multi-Channel SDR. Military Communication and Information Systems Conference, MCC 2010, Sep 2010, Wroclaw, Poland. pp.1-7. ⟨ujm-00552208⟩

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