Complete activation scheme for IP design protection - Université Jean-Monnet-Saint-Étienne Access content directly
Conference Papers Year : 2017

Complete activation scheme for IP design protection


—Intellectual Property (IP) illegal copying is a major threat in today's integrated circuits industry which is massively based on a design-and-reuse paradigm. In order to fight this threat, a designer must track how many times an IP has been instantiated. Moreover, illegal copies of an IP must be unusable. We propose a hardware/software scheme which allows a designer to remotely activate an IP with minimal area overhead. The software modifies the IP efficiently and can handle very large netlists. Unique identification of hardware instances is achieved by integrating a TERO-PUF along with a lightweight key reconciliation module. A cryptographic core guarantees security and triggers a logic locking/masking module which makes the IP unusable unless the correct encrypted activation word is applied. The hardware side is implemented on several FPGAs. I. GOAL OF THE DEMO The goal of the proposed hardware demo is to show how a designer can modify an IP so that it can be activated remotely and securely. Before activation, the IP can be instantiated but is unusable. Its outputs are either forced to a fixed logic value or disturbed. Later, upon activation request, the designer sends an encrypted activation word. This is then decrypted inside the IP to activate it. Each IP instance is made unique by integrating a PUF, leveraged to derive a secret key. It prevents a malicious system integrator from instantiating the IP on a non-trusted hardware target. We make the whole system open-source. II. EXPERIMENTAL SETUP From a hardware perspective, the experimental setup (Fig. 1) comprises a laptop and an FPGA board, connected via a serial interface. A user interface can perform the following actions: • Modify the IP, using logic masking [1] or logic locking [2] to make it controllably unusable. Several parameters can be tuned, as well as the area overhead. • Obtain the reference response from the TERO-PUF [3] during the enrolment phase. • Reconcile the key with CASCADE [4] and activate the IP. III. DEMO SCENARIO AND OBSERVABLES The typical demo scenario is the following. First, an IP in the form of a netlist is modified and the associated activation word (AW) is stored. The motherboard is then connected to the PC and the daughter-board is enrolled by obtaining a response from a PUF instantiated at a known location. This response is used to encrypt AW. The protected IP is instantiated on the enrolled daughter-board. Before activation, the IP does not operate correctly. When the activation phase starts, the key reconciliation procedure is conducted to ensure that the PUF response generated on the daughter-board is identical to the one obtained during enrollment. Then, AW is encrypted and sent to the board. It is then internally decrypted and sent to the logic masking/locking module, to make the IP fully operational. If the IP is instantiated on a different daughter-board, it does not operate correctly since the PUF response is different. Each IP is then securely bound to a trusted hardware target.
Fichier principal
Vignette du fichier
2017_HOST_hwdemo_colombier.pdf (160.23 Ko) Télécharger le fichier
Origin : Files produced by the author(s)

Dates and versions

ujm-01575569 , version 1 (21-08-2017)


  • HAL Id : ujm-01575569 , version 1


Brice Colombier, Ugo Mureddu, Marek Laban, Oto Petura, Lilian Bossuet, et al.. Complete activation scheme for IP design protection. IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2017, MCLEAN, VIRGINIA, United States. ⟨ujm-01575569⟩
83 View
59 Download


Gmail Facebook X LinkedIn More